mirror of https://github.com/YosysHQ/yosys.git
d84c3a9eac
Drop use_selection flag from Json and Jny Writers, instead they always operate on selections and if the write_* pass is called without -selected then it pushes the complete selection. rtlil_backend prints differently if it is dumping a portion or whole design, so push the complete selection inside of the dump if needed. Also update `Design::selected_modules()` error message for partially selected modules to match the existing error messages that it replaces. |
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| .. | ||
| aiger | ||
| aiger2 | ||
| blif | ||
| btor | ||
| cxxrtl | ||
| edif | ||
| firrtl | ||
| functional | ||
| intersynth | ||
| jny | ||
| json | ||
| rtlil | ||
| simplec | ||
| smt2 | ||
| smv | ||
| spice | ||
| table | ||
| verilog | ||