mirror of https://github.com/YosysHQ/yosys.git
171c425cf9
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) |
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| .. | ||
| .gitignore | ||
| autotest.mk | ||
| autotest.sh | ||
| cmp_tbdata.c | ||
| profiler.pl | ||
| txt2tikztiming.py | ||
| vcd2txt.pl | ||
| vcdcd.pl | ||