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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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e2f6d61c00
yosys
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frontends
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Clifford Wolf
5328a85149
Do not set "nosync" on task outputs,
fixes
#134
2016-03-24 12:16:47 +01:00
..
ast
Do not set "nosync" on task outputs,
fixes
#134
2016-03-24 12:16:47 +01:00
blif
Fixed BLIF parser for empty port assignments
2016-02-24 09:16:43 +01:00
ilang
Fixed oom bug in ilang parser
2015-11-29 20:30:32 +01:00
liberty
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
verific
Support for more Verific primitives (patch I got per email)
2016-02-13 08:19:30 +01:00
verilog
Fixed Verilog parser fix and more similar improvements
2016-03-15 12:22:31 +01:00
vhdl2verilog
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00