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tests
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
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.gitignore
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Initialization support for all iCE40 bram modes
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2015-04-26 08:39:31 +02:00 |
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Makefile.inc
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ice40: split out cells_map.v into ff_map.v
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2020-05-14 10:33:56 -07:00 |
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abc9_model.v
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ice40: specify fixes
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2020-02-27 10:17:29 -08:00 |
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arith_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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brams.txt
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ice40: match memory inference attribute values case insensitive.
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2020-02-06 14:58:20 +00:00 |
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brams_init.py
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Switched to Python 3
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2015-08-22 09:59:33 +02:00 |
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brams_map.v
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28 16:23:40 -08:00 |
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cells_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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cells_sim.v
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Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
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2020-06-14 00:45:22 -07:00 |
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dsp_map.v
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
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2019-08-08 12:56:05 -07:00 |
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ff_map.v
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ice40: split out cells_map.v into ff_map.v
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2020-05-14 10:33:56 -07:00 |
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ice40_braminit.cc
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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2020-04-02 09:51:32 -07:00 |
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ice40_ffinit.cc
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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2020-04-02 09:51:32 -07:00 |
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ice40_ffssr.cc
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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2020-04-02 09:51:32 -07:00 |
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ice40_opt.cc
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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2020-04-02 09:51:32 -07:00 |
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latches_map.v
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Added synth_ice40 support for latches via logic loops
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2016-05-06 23:02:37 +02:00 |
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synth_ice40.cc
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xilinx/ice40/ecp5: zinit requires selected wires, so select them all
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2020-05-14 10:33:56 -07:00 |
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