yosys/tests
Clifford Wolf 4c38ec1cc8 Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
..
asicworld Added note to "make test": use git checkout of iverilog 2014-07-16 10:03:07 +02:00
hana Added note to "make test": use git checkout of iverilog 2014-07-16 10:03:07 +02:00
memories Added SAT-based write-port sharing to memory_share 2014-07-19 15:33:55 +02:00
realmath Added note to "make test": use git checkout of iverilog 2014-07-16 10:03:07 +02:00
sat now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
share Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
simple Implemented dynamic bit-/part-select for memory writes 2014-07-17 16:49:23 +02:00
techmap Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface 2014-07-16 14:08:51 +02:00
tools Also simulate unmapped memories in "make test" 2014-07-17 16:53:52 +02:00
vloghtb Added tests/vloghtb/test_share.sh 2014-07-20 15:33:05 +02:00