mirror of https://github.com/YosysHQ/yosys.git
119 lines
1.9 KiB
Verilog
119 lines
1.9 KiB
Verilog
module split_shiftx_test01(i, s, o);
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wire [3:0] _0_;
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input [8:0] i;
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output [2:0] o;
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input [1:0] s;
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\$macc #(
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.A_WIDTH(32'd4),
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.B_WIDTH(32'd0),
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.CONFIG(10'h282),
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.CONFIG_WIDTH(32'd10),
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.Y_WIDTH(32'd4)
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) _1_ (
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.A({ 2'h3, s }),
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.B(),
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.Y(_0_)
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);
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\$shiftx #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd9),
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.B_SIGNED(32'd1),
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.B_WIDTH(32'd5),
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.Y_WIDTH(32'd3)
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) _2_ (
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.A(i),
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.B({ 1'h0, _0_ }),
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.Y(o)
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);
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endmodule
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// Sign bit is 1
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module split_shiftx_test02(i, s, o);
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wire [3:0] _0_;
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input [8:0] i;
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output [2:0] o;
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input [1:0] s;
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\$macc #(
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.A_WIDTH(32'd4),
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.B_WIDTH(32'd0),
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.CONFIG(10'h282),
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.CONFIG_WIDTH(32'd10),
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.Y_WIDTH(32'd4)
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) _1_ (
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.A({ 2'h3, s }),
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.B(),
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.Y(_0_)
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);
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\$shiftx #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd9),
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.B_SIGNED(32'd1),
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.B_WIDTH(32'd5),
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.Y_WIDTH(32'd3)
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) _2_ (
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.A(i),
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.B({ 1'h1, _0_ }),
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.Y(o)
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);
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endmodule
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// Non constant $macc
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module split_shiftx_test03(i, s, o);
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wire [3:0] _0_;
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input [8:0] i;
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output [2:0] o;
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input [1:0] s;
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\$macc #(
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.A_WIDTH(32'd4),
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.B_WIDTH(32'd0),
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.CONFIG(10'h282),
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.CONFIG_WIDTH(32'd10),
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.Y_WIDTH(32'd4)
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) _1_ (
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.A({ s, s }),
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.B(),
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.Y(_0_)
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);
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\$shiftx #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd9),
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.B_SIGNED(32'd1),
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.B_WIDTH(32'd5),
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.Y_WIDTH(32'd3)
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) _2_ (
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.A(i),
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.B({ 1'h0, _0_ }),
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.Y(o)
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);
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endmodule
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// Wrong constant $macc
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module split_shiftx_test04(i, s, o);
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wire [3:0] _0_;
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input [8:0] i;
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output [2:0] o;
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input [1:0] s;
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\$macc #(
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.A_WIDTH(32'd4),
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.B_WIDTH(32'd0),
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.CONFIG(10'h282),
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.CONFIG_WIDTH(32'd10),
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.Y_WIDTH(32'd4)
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) _1_ (
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.A({ 2'h2, s }),
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.B(),
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.Y(_0_)
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);
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\$shiftx #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd9),
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.B_SIGNED(32'd1),
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.B_WIDTH(32'd5),
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.Y_WIDTH(32'd3)
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) _2_ (
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.A(i),
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.B({ 1'h0, _0_ }),
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.Y(o)
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);
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endmodule
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