mirror of https://github.com/YosysHQ/yosys.git
68 lines
1.4 KiB
Bash
68 lines
1.4 KiB
Bash
#!/bin/bash
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set -ex
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XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
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XILINX_PART=xc6slx9-2-tqg144
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../../../yosys - << EOT
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# read design
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read_verilog example.v
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# high-level synthesis
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hierarchy -check -top top
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proc; opt; fsm; opt; techmap; opt
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# mapping logic to LUTs using Berkeley ABC
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abc -lut 6; opt
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# map internal cells to FPGA cells
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techmap -map ../cells.v; opt
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# insert i/o buffers
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iopadmap -outpad OBUF I:O -inpad BUFGP O:I
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# write netlist
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write_edif synth.edif
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EOT
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cat > bitgen.ut <<- EOT
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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:No
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-g DriveDone:No
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-g en_sw_gsr:No
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-g drive_awake:No
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-g sw_clk:Startupclk
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-g sw_gwe_cycle:5
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-g sw_gts_cycle:4
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EOT
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$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
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$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
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$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
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$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
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$XILINX_DIR/bin/lin64/bitgen -f bitgen.ut placed.ncd example.bit constraints.pcf
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