Clifford Wolf a9fefc6ce1 Bugfixes for empty signal vectors		2013-07-10 12:52:29 +02:00
..
abc	Added support for "assign" statements in abc vlparse	2013-06-15 13:50:38 +02:00
cmds	Added renaming of wires and cells to "rename" command	2013-06-19 16:55:43 +02:00
dfflibmap	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	2013-03-27 10:51:15 +01:00
extract	Split extract -attr into extract -cell_attr and -wire_attr	2013-03-08 08:19:24 +01:00
fsm	Renamed opt_rmunused to opt_clean	2013-06-05 07:07:31 +02:00
hierarchy	Improved log messages generated by hierarchy pass	2013-05-26 12:20:51 +02:00
memory	Added -nomap option to memory pass	2013-03-21 09:11:06 +01:00
opt	Bugfixes for empty signal vectors	2013-07-10 12:52:29 +02:00
proc	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
sat	Added SAT support for -all/-max with -verify	2013-06-23 13:28:30 +02:00
scc	fixed typos	2013-03-18 07:28:31 +01:00
submod	Renamed opt_rmunused to opt_clean	2013-06-05 07:07:31 +02:00
techmap	Fixed techmap/flatten for positional module arguments	2013-05-26 12:21:17 +02:00