yosys/frontends/verilog
whitequark ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
preproc.cc verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l Merge pull request #2179 from splhack/static-cast 2020-07-01 16:40:20 +02:00
verilog_parser.y Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00