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.gitignore
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
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Makefile.inc
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
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abc_5g.box
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
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abc_5g.lut
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ecp5: Add abc9 option
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2019-06-14 17:15:02 +01:00 |
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abc_5g_nowide.lut
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Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
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abc_map.v
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ecp5 to use -max_iter 1
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2019-08-20 19:18:36 -07:00 |
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abc_model.v
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
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abc_unmap.v
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ecp5: remove DPR16X4 from abc_unmap.v
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2019-08-20 19:20:17 -07:00 |
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arith_map.v
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ecp5: Improve mapping of $alu when BI is used
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2019-06-21 09:45:11 +01:00 |
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bram.txt
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
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brams_connect.py
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ecp5: Script for BRAM IO connections
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2018-10-10 16:11:00 +01:00 |
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brams_init.py
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
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brams_map.v
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ecp5: Disable LSR inversion
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2018-10-16 12:48:39 +01:00 |
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cells_bb.v
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ecp5: Add DDRDLLA
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2019-02-19 19:34:37 +00:00 |
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cells_map.v
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
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cells_sim.v
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-23 11:26:55 -07:00 |
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ecp5_ffinit.cc
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ecp5: Demote conflicting FF init values to a warning
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2019-03-04 11:26:20 +00:00 |
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latches_map.v
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ecp5: Add latch inference
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2018-10-19 15:16:40 +01:00 |
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lutram.txt
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synth_ecp5: rename dram to lutram everywhere.
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2019-07-16 20:45:12 +00:00 |
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lutrams_map.v
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synth_ecp5: rename dram to lutram everywhere.
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2019-07-16 20:45:12 +00:00 |
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synth_ecp5.cc
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ecp5 to use -max_iter 1
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2019-08-20 19:18:36 -07:00 |
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