mirror of https://github.com/YosysHQ/yosys.git
7f0548c16f
Signed-off-by: Clifford Wolf <clifford@clifford.at> |
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| .. | ||
| .gitignore | ||
| README | ||
| cmos_cells.lib | ||
| cmos_cells.sp | ||
| cmos_cells.v | ||
| cmos_cells_digital.sp | ||
| counter.v | ||
| counter.ys | ||
| counter_digital.ys | ||
| counter_tb.gtkw | ||
| counter_tb.v | ||
| testbench.sh | ||
| testbench.sp | ||
| testbench_digital.sh | ||
| testbench_digital.sp | ||
README
In this directory contains an example for generating a spice output using two different spice modes, normal analog transient simulation and event-driven digital simulation as supported by ngspice xspice sub-module. Each test bench can be run separately by either running: - testbench.sh, to start analog simulation or - testbench_digital.sh for mixed-signal digital simulation. The later case also includes pure verilog simulation using the iverilog and gtkwave for comparison.