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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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cd9407404a
yosys
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passes
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Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
..
abc
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
cmds
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
fsm
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
hierarchy
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
memory
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
opt
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
proc
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
sat
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
techmap
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
tests
Added "techmap -assert"
2014-07-31 02:21:41 +02:00