mirror of https://github.com/YosysHQ/yosys.git
f8325f66b7
If the `$ge` cell we are replacing has wide output port, the upper bits on the port should be driven to zero. That's not what a `$not` cell with a single-bit input does. Instead opt for a `$logic_not` cell, which does zero-pad its output. Fixes #3867. |
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| opt | ||
| pmgen | ||
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| techmap | ||
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