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yosys
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cb1d439d10
yosys
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passes
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Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
..
cmds
More intuitive handling of "cd .." for singleton modules
2017-08-19 00:15:12 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Minor changes to opt_demorgan requested during code review
2017-09-14 10:35:25 -07:00
proc
Add src attribute to extra cells generated by proc_dlatch
2017-09-09 10:18:08 +02:00
sat
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
techmap
Added missing "break"
2017-09-15 17:54:52 -07:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00