yosys/techlibs/efinix
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
..
Makefile.inc Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
arith_map.v Fix formating 2019-08-11 17:05:24 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_map.v one bit enable signal 2019-08-11 13:59:39 +02:00
cells_map.v Add missing latch mapping 2019-10-04 12:58:11 +02:00
cells_sim.v FF should be initialized to 0 2019-10-04 13:27:10 +02:00
efinix_fixcarry.cc Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
efinix_gbuf.cc clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
synth_efinix.cc Merge pull request #1604 from whitequark/unify-ram-naming 2020-01-02 21:06:17 +00:00