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yosys/passes
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Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
..
cmds qwp: remove 2024-10-25 14:09:58 +01:00
equiv equiv_simple: Take FFs into account for driver map 2024-02-21 12:05:52 +01:00
fsm rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hierarchy rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
memory rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
opt rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
pmgen rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
proc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
sat rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
techmap cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
tests rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00