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yosys/techlibs
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Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
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cmos Improved liberty file test case 2015-07-06 17:45:56 +02:00
common Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
ice40 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
xilinx Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00