Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-04-18 17:45:47 +02:00
..
Makefile.inc	Added edif backend (still under construction)	2013-08-22 11:34:55 +02:00
edif.cc	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
runtest.py	Add generation of logic cells to EDIF back-end runtest.py	2017-03-19 14:57:40 +01:00