mirror of https://github.com/YosysHQ/yosys.git
b98376884e
These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine. |
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| .. | ||
| anlogic | ||
| common | ||
| ecp5 | ||
| efinix | ||
| gowin | ||
| ice40 | ||
| intel_alm | ||
| machxo2 | ||
| nexus | ||
| quicklogic | ||
| xilinx | ||
| run-test.sh | ||