yosys/frontends
Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
..
aiger Provide an integer implementation of decimal_digits(). 2021-02-01 11:23:44 -08:00
ast verilog: impose limit on maximum expression width 2021-03-04 15:20:52 -05:00
blif Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
json frontend: json: parse negative values 2021-02-23 00:26:11 +01:00
liberty Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: remove dotted identifiers. 2020-11-25 16:47:20 +00:00
verific Update README 2021-03-04 16:43:30 +01:00
verilog verilog: fix sizing of ports with int types in module headers 2021-03-01 13:39:05 -05:00