yosys/passes
Amelia Cuss bf4a46ccb3 proc_rom: don't assert on big actionless switch.
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
2024-02-18 01:33:28 +11:00
..
cmds Update passes/cmds/stat.cc 2024-02-16 07:44:09 -08:00
equiv equiv_simple: Fix seed handling in non-short mode 2023-10-03 13:05:42 +02:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy hierarchy: Without a known top module, derive all deferred modules 2024-02-06 10:31:40 +01:00
memory Fix printf formats 2024-01-15 12:07:54 +01:00
opt Merge pull request #4084 from jix/scopeinfo 2024-02-12 09:51:22 +01:00
pmgen Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
proc proc_rom: don't assert on big actionless switch. 2024-02-18 01:33:28 +11:00
sat clk2fflogic: Fix handling of $check cells 2024-02-14 11:42:27 +01:00
techmap Merge pull request #4084 from jix/scopeinfo 2024-02-12 09:51:22 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00