yosys/techlibs/common
Ahmed Irfan 06482c046b Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-03 10:54:54 +01:00
..
Makefile.inc Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
blackbox.sed Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
pmux2mux.v btor 2014-01-03 10:52:44 +01:00
simcells.v Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
simlib.v Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
stdcells.v Various small cleanups in stdcells.v techmap code 2013-12-31 15:41:40 +01:00