yosys/passes
Clifford Wolf b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
..
abc Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
cmds Added "trace" command 2014-07-31 15:02:16 +02:00
fsm Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
hierarchy Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
memory Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
opt Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
proc Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
sat Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
techmap Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
tests Added "techmap -assert" 2014-07-31 02:21:41 +02:00