Patrick Urban 81964d6d6f synth_gatemate: Update pass ... * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style		2021-11-13 21:53:25 +01:00
..
anlogic	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
common	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
ecp5	abc9: replace cell type/parameters if derived type already processed (#2991)	2021-09-09 10:05:55 -07:00
efinix	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
gatemate	synth_gatemate: Update pass	2021-11-13 21:53:25 +01:00
gowin	Gowin: deal with active-low tristate (#2971)	2021-08-20 21:21:06 +02:00
ice40	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	2021-08-11 14:52:38 +02:00
intel_alm	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
machxo2	iopadmap: Add native support for negative-polarity output enable.	2021-11-09 15:40:16 +01:00
nexus	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
quicklogic	quicklogic: ABC9 synthesis	2021-04-17 20:54:58 +02:00
xilinx	FfData: some refactoring.	2021-10-07 04:24:06 +02:00
run-test.sh	Add default assignments to SB_LUT4	2021-04-20 12:46:21 +02:00