yosys/techlibs/common
Clifford Wolf b41740060b Fixed techmap of $gt and $ge with multi-bit outputs 2013-11-06 22:59:45 +01:00
..
Makefile.inc Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
blackbox.sed Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
simlib.v Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
stdcells.v Fixed techmap of $gt and $ge with multi-bit outputs 2013-11-06 22:59:45 +01:00
stdcells_sim.v Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ 2013-10-18 12:13:34 +02:00