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9 lines
416 B
Plaintext
9 lines
416 B
Plaintext
read_verilog ../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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