yosys/tests/arch/intel_alm/add_sub.ys

read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6). 2019-11-19 04:19:00 -06:00			`read_verilog ../common/add_sub.v`
			`hierarchy -top top`
			`equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
			`cd top # Constrain all select calls below inside the top module`
			`stat`
			`select -assert-count 8 t:MISTRAL_ALUT_ARITH`
			`select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D`