mirror of https://github.com/YosysHQ/yosys.git
526 lines
13 KiB
Verilog
526 lines
13 KiB
Verilog
module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [71:0] A1DATA;
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input [8:0] B1ADDR;
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input [71:0] B1DATA;
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input [7:0] B1EN;
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wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
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wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
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wire [7:0] DIP, DOP;
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wire [63:0] DI, DO;
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wire [71:0] A1DATA_BUF;
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reg [71:0] B1DATA_Q;
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reg [7:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
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assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
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assign A1DATA[44:36] = transparent_cycle[4] ? B1DATA_Q[44:36] : A1DATA_BUF[44:36];
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assign A1DATA[53:45] = transparent_cycle[5] ? B1DATA_Q[53:45] : A1DATA_BUF[53:45];
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assign A1DATA[62:54] = transparent_cycle[6] ? B1DATA_Q[62:54] : A1DATA_BUF[62:54];
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assign A1DATA[71:63] = transparent_cycle[7] ? B1DATA_Q[71:63] : A1DATA_BUF[71:63];
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assign A1DATA_BUF = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
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DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
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DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB36E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(72),
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.WRITE_WIDTH_B(72),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[63:32]),
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.DOADO(DO[31:0]),
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.DOPBDOP(DOP[7:4]),
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.DOPADOP(DOP[3:0]),
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.DIBDI(DI[63:32]),
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.DIADI(DI[31:0]),
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.DIPBDIP(DIP[7:4]),
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.DIPADIP(DIP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [35:0] A1DATA;
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input [8:0] B1ADDR;
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input [35:0] B1DATA;
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input [3:0] B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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wire [35:0] A1DATA_BUF;
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reg [35:0] B1DATA_Q;
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reg [3:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
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assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
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assign A1DATA_BUF = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.WRITE_WIDTH_B(36),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[31:16]),
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.DOADO(DO[15:0]),
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.DOPBDOP(DOP[3:2]),
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.DOPADOP(DOP[1:0]),
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.DIBDI(DI[31:16]),
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.DIADI(DI[15:0]),
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.DIPBDIP(DIP[3:2]),
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.DIPADIP(DIP[1:0]),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [9:0] A1ADDR;
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output [17:0] A1DATA;
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input [9:0] B1ADDR;
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input [17:0] B1DATA;
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input [1:0] B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 4'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 4'b0};
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [17:0] A1DATA_BUF;
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reg [17:0] B1DATA_Q;
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reg [1:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(18),
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.READ_WIDTH_B(18),
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.WRITE_WIDTH_A(18),
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.WRITE_WIDTH_B(18),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[15:0]),
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.DOPADOP(DOP[1:0]),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI[15:0]),
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.DIPBDIP(DIP[1:0]),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({2'b00, B1EN})
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [10:0] A1ADDR;
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output [8:0] A1DATA;
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input [10:0] B1ADDR;
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input [8:0] B1DATA;
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input B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [8:0] A1DATA_BUF;
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reg [8:0] B1DATA_Q;
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reg transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(9),
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.READ_WIDTH_B(9),
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.WRITE_WIDTH_A(9),
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.WRITE_WIDTH_B(9),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({3'b00, B1EN})
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [11:0] A1ADDR;
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output [3:0] A1DATA;
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input [11:0] B1ADDR;
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input [3:0] B1DATA;
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input B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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reg transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(4),
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.READ_WIDTH_B(4),
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.WRITE_WIDTH_A(4),
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.WRITE_WIDTH_B(4),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({3'b00, B1EN})
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [12:0] A1ADDR;
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output [1:0] A1DATA;
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input [12:0] B1ADDR;
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input [1:0] B1DATA;
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input B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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reg transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(2),
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.READ_WIDTH_B(2),
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.WRITE_WIDTH_A(2),
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.WRITE_WIDTH_B(2),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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|
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
|
|
.ENARDEN(|1),
|
|
.REGCEAREGCE(|1),
|
|
.RSTRAMARSTRAM(|0),
|
|
.RSTREGARSTREG(|0),
|
|
.WEA(2'b0),
|
|
|
|
.DIBDI({8'b0, DI}),
|
|
.DIPBDIP({1'b0, DIP}),
|
|
.ADDRBWRADDR(B1ADDR_14),
|
|
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
|
|
.ENBWREN(|1),
|
|
.REGCEB(|0),
|
|
.RSTRAMB(|0),
|
|
.RSTREGB(|0),
|
|
.WEBWE({3'b00, B1EN})
|
|
);
|
|
endmodule
|
|
|
|
// ------------------------------------------------------------------------
|
|
|
|
module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
|
parameter TRANSP2 = 1;
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|
parameter CLKPOL2 = 1;
|
|
parameter CLKPOL3 = 1;
|
|
|
|
input CLK2;
|
|
input CLK3;
|
|
|
|
input [13:0] A1ADDR;
|
|
output A1DATA;
|
|
|
|
input [13:0] B1ADDR;
|
|
input B1DATA;
|
|
input B1EN;
|
|
|
|
wire [13:0] A1ADDR_14 = A1ADDR;
|
|
wire [13:0] B1ADDR_14 = B1ADDR;
|
|
|
|
wire DIP, DOP;
|
|
wire [7:0] DI, DO;
|
|
|
|
wire [3:0] A1DATA_BUF;
|
|
reg [3:0] B1DATA_Q;
|
|
reg transparent_cycle;
|
|
|
|
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
|
|
|
|
generate if (CLKPOL2)
|
|
always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
|
else
|
|
always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
|
endgenerate
|
|
|
|
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
|
|
|
|
assign A1DATA_BUF = { DOP, DO };
|
|
assign { DIP, DI } = B1DATA;
|
|
|
|
RAMB18E1 #(
|
|
.RAM_MODE("TDP"),
|
|
.READ_WIDTH_A(1),
|
|
.READ_WIDTH_B(1),
|
|
.WRITE_WIDTH_A(1),
|
|
.WRITE_WIDTH_B(1),
|
|
.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
|
|
.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
|
|
) _TECHMAP_REPLACE_ (
|
|
.DIADI(16'b0),
|
|
.DIPADIP(2'b0),
|
|
.DOADO(DO[7:0]),
|
|
.DOPADOP(DOP),
|
|
.ADDRARDADDR(A1ADDR_14),
|
|
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
|
|
.ENARDEN(|1),
|
|
.REGCEAREGCE(|1),
|
|
.RSTRAMARSTRAM(|0),
|
|
.RSTREGARSTREG(|0),
|
|
.WEA(2'b0),
|
|
|
|
.DIBDI({8'b0, DI}),
|
|
.DIPBDIP({1'b0, DIP}),
|
|
.ADDRBWRADDR(B1ADDR_14),
|
|
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
|
|
.ENBWREN(|1),
|
|
.REGCEB(|0),
|
|
.RSTRAMB(|0),
|
|
.RSTREGB(|0),
|
|
.WEBWE({3'b00, B1EN})
|
|
);
|
|
endmodule
|
|
|