mirror of https://github.com/YosysHQ/yosys.git
12 lines
561 B
Plaintext
12 lines
561 B
Plaintext
read_verilog ../common/add_sub.v
|
|
hierarchy -top top
|
|
equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 2 t:LUT2
|
|
select -assert-count 8 t:LUT3
|
|
select -assert-count 2 t:LUT4
|
|
select -assert-count 8 t:inpad
|
|
select -assert-count 8 t:outpad
|
|
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
|