yosys/passes
Martin Povišer d6566eb344 booth: Redo baseline architecture summation
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
2023-11-22 15:47:11 +01:00
..
cmds Merge pull request #3946 from rmlarsen/toposort 2023-10-17 13:00:18 +01:00
equiv Merge pull request #3126 from georgerennie/equiv_make_assertions 2023-02-14 17:15:55 +01:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
opt Merge pull request #3946 from rmlarsen/toposort 2023-10-17 13:00:18 +01:00
pmgen peepopt: Add assert of consistent `shiftadd` data 2023-11-06 16:35:00 +01:00
proc proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
sat Merge pull request #3986 from povik/sim-ui-fixes 2023-10-16 16:54:05 +02:00
techmap booth: Redo baseline architecture summation 2023-11-22 15:47:11 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00