yosys/passes
Eddie Hung ac2fc3a144
Merge pull request #1264 from YosysHQ/eddie/fix_1254
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
2019-08-08 07:58:33 -07:00
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cmds Tweak default gate costs, cleanup "stat -tech cmos" 2019-08-07 10:25:51 +02:00
equiv Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Use input default values in hierarchy pass 2019-06-19 11:49:20 +02:00
memory Error out if enable > dbits 2019-07-13 03:39:23 -07:00
opt opt_lut to ignore LUT cells, or those that drive bits, with (* keep *) 2019-08-07 13:15:02 -07:00
pmgen Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
proc proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
sat Fix tests/various/async FFL test 2019-07-09 22:44:39 +02:00
techmap Add comment 2019-08-07 09:54:27 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00