mirror of https://github.com/YosysHQ/yosys.git
492 lines
13 KiB
Verilog
492 lines
13 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// See Xilinx UG953 and UG474 for a description of the cell types below.
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// http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
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// http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
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module VCC(output P);
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assign P = 1;
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endmodule
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module GND(output G);
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assign G = 0;
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endmodule
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module IBUF(
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output O,
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(* iopad_external_pin *)
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input I);
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parameter IOSTANDARD = "default";
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parameter IBUF_LOW_PWR = 0;
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assign O = I;
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endmodule
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module OBUF(
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(* iopad_external_pin *)
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output O,
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input I);
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parameter IOSTANDARD = "default";
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parameter DRIVE = 12;
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parameter SLEW = "SLOW";
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assign O = I;
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endmodule
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module BUFG(
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(* clkbuf_driver *)
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output O,
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input I);
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assign O = I;
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endmodule
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module BUFGCTRL(
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(* clkbuf_driver *)
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output O,
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input I0, input I1,
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input S0, input S1,
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input CE0, input CE1,
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input IGNORE0, input IGNORE1);
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parameter [0:0] INIT_OUT = 1'b0;
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parameter PRESELECT_I0 = "FALSE";
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parameter PRESELECT_I1 = "FALSE";
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parameter [0:0] IS_CE0_INVERTED = 1'b0;
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parameter [0:0] IS_CE1_INVERTED = 1'b0;
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parameter [0:0] IS_S0_INVERTED = 1'b0;
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parameter [0:0] IS_S1_INVERTED = 1'b0;
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parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
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parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
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wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
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wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
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wire S0_true = (S0 ^ IS_S0_INVERTED);
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wire S1_true = (S1 ^ IS_S1_INVERTED);
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assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
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endmodule
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module BUFHCE(
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(* clkbuf_driver *)
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output O,
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input I,
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input CE);
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parameter [0:0] INIT_OUT = 1'b0;
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parameter CE_TYPE = "SYNC";
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parameter [0:0] IS_CE_INVERTED = 1'b0;
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assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
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endmodule
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// module OBUFT(output O, input I, T);
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// assign O = T ? 1'bz : I;
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// endmodule
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// module IOBUF(inout IO, output O, input I, T);
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// assign O = IO, IO = T ? 1'bz : I;
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// endmodule
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module INV(output O, input I);
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assign O = !I;
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endmodule
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O6 = I0 ? s1[1] : s1[0];
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wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
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wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
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wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
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assign O5 = I0 ? s5_1[1] : s5_1[0];
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endmodule
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module MUXCY(output O, input CI, DI, S);
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assign O = S ? CI : DI;
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endmodule
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(* abc_box_id = 1, lib_whitebox *)
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module MUXF7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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(* abc_box_id = 2, lib_whitebox *)
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module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module XORCY(output O, input CI, LI);
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assign O = CI ^ LI;
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endmodule
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(* abc_box_id = 4, lib_whitebox *)
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module CARRY4(
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(* abc_carry *)
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output [3:0] CO,
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output [3:0] O,
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(* abc_carry *)
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input CI,
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input CYINIT,
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input [3:0] DI, S
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);
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assign O = S ^ {CO[2:0], CI | CYINIT};
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assign CO[0] = S[0] ? CI | CYINIT : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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endmodule
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`ifdef _EXPLICIT_CARRY
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module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
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parameter CYINIT_FABRIC = 0;
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wire CI_COMBINE;
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if(CYINIT_FABRIC) begin
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assign CI_COMBINE = CI_INIT;
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end else begin
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assign CI_COMBINE = CI;
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end
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assign CO_CHAIN = S ? CI_COMBINE : DI;
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assign CO_FABRIC = S ? CI_COMBINE : DI;
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assign O = S ^ CI_COMBINE;
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endmodule
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module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
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assign CO_CHAIN = S ? CI : DI;
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assign CO_FABRIC = S ? CI : DI;
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assign O = S ^ CI;
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endmodule
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`endif
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
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module FDRE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDSE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDCE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDPE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDRE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
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endmodule
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module FDSE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
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endmodule
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module FDCE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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module FDPE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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endmodule
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module RAM32X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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parameter INIT = 32'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
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reg [31:0] mem = INIT;
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assign SPO = mem[a];
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assign DPO = mem[dpra];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM64X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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wire [5:0] a = {A5, A4, A3, A2, A1, A0};
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wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
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reg [63:0] mem = INIT;
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assign SPO = mem[a];
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assign DPO = mem[dpra];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM128X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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input WCLK,
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input WE,
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input [6:0] A, DPRA
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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reg [127:0] mem = INIT;
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assign SPO = mem[A];
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assign DPO = mem[DPRA];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[A] <= D;
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc_arrival=1472 *)
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output Q,
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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input CLK,
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input D
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|
);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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|
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reg [15:0] r = INIT;
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assign Q = r[{A3,A2,A1,A0}];
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generate
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if (IS_CLK_INVERTED) begin
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always @(negedge CLK) if (CE) r <= { r[14:0], D };
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end
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else
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always @(posedge CLK) if (CE) r <= { r[14:0], D };
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endgenerate
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endmodule
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|
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module SRLC16E (
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output Q,
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|
output Q15,
|
|
input A0, A1, A2, A3, CE,
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|
(* clkbuf_sink *)
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|
input CLK,
|
|
input D
|
|
);
|
|
parameter [15:0] INIT = 16'h0000;
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|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
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|
|
|
reg [15:0] r = INIT;
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|
assign Q15 = r[15];
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|
assign Q = r[{A3,A2,A1,A0}];
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|
generate
|
|
if (IS_CLK_INVERTED) begin
|
|
always @(negedge CLK) if (CE) r <= { r[14:0], D };
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|
end
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|
else
|
|
always @(posedge CLK) if (CE) r <= { r[14:0], D };
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|
endgenerate
|
|
endmodule
|
|
|
|
module SRLC32E (
|
|
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
|
(* abc_arrival=1472 *)
|
|
output Q,
|
|
(* abc_arrival=1114 *)
|
|
output Q31,
|
|
input [4:0] A,
|
|
input CE,
|
|
(* clkbuf_sink *)
|
|
input CLK,
|
|
input D
|
|
);
|
|
parameter [31:0] INIT = 32'h00000000;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
|
|
reg [31:0] r = INIT;
|
|
assign Q31 = r[31];
|
|
assign Q = r[A];
|
|
generate
|
|
if (IS_CLK_INVERTED) begin
|
|
always @(negedge CLK) if (CE) r <= { r[30:0], D };
|
|
end
|
|
else
|
|
always @(posedge CLK) if (CE) r <= { r[30:0], D };
|
|
endgenerate
|
|
endmodule
|