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riscv
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yosys
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a721f7d768
yosys
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passes
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Clifford Wolf
309ae98246
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
2014-07-18 10:28:45 +02:00
..
abc
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
2014-03-12 23:17:14 +01:00
cmds
Added %D and %c select commands
2014-06-14 16:19:32 +02:00
fsm
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
2014-03-11 14:24:24 +01:00
hierarchy
fixed cell array handling of positional arguments
2014-06-07 12:17:11 +02:00
memory
Changes to "memory" pass for new $memwr/$mem WR_EN interface
2014-07-16 12:49:50 +02:00
opt
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
2014-07-18 10:28:45 +02:00
proc
Do not create $dffsr cells with no-op resets in proc_dff
2014-06-19 12:29:29 +02:00
sat
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
techmap
Added support for "blackbox" attribute to iopadmap
2014-07-17 08:59:07 +02:00