mirror of https://github.com/YosysHQ/yosys.git
131 lines
2.2 KiB
Verilog
131 lines
2.2 KiB
Verilog
`default_nettype none
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(* abc9_box *)
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module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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`ifdef cyclonev
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specify
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(A *> Y) = 3732;
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(B *> Y) = 3928;
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endspecify
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`endif
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`ifdef arriav
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// NOTE: Arria V appears to have only one set of timings for all DSP modes...
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specify
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(A *> Y) = 1895;
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(B *> Y) = 2053;
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endspecify
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`endif
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`ifdef cyclone10gx
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 3732;
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(B *> Y) = 3928;
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endspecify
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`endif
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wire [53:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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`ifdef cyclonev
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specify
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(A *> Y) = 3180;
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(B *> Y) = 3982;
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endspecify
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`endif
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`ifdef arriav
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// NOTE: Arria V appears to have only one set of timings for all DSP modes...
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specify
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(A *> Y) = 1895;
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(B *> Y) = 2053;
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endspecify
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`endif
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`ifdef cyclone10gx
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 3180;
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(B *> Y) = 3982;
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endspecify
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`endif
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wire [35:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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`ifdef cyclonev
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specify
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(A *> Y) = 2818;
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(B *> Y) = 3051;
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endspecify
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`endif
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`ifdef arriav
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// NOTE: Arria V appears to have only one set of timings for all DSP modes...
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specify
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(A *> Y) = 1895;
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(B *> Y) = 2053;
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endspecify
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`endif
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`ifdef cyclone10gx
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 2818;
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(B *> Y) = 3051;
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endspecify
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`endif
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wire [17:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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