yosys/passes
Clifford Wolf c616802ac7 Always use BLIF as ABC output format 2013-12-31 13:41:16 +01:00
..
abc Always use BLIF as ABC output format 2013-12-31 13:41:16 +01:00
cmds Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
extract Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
fsm Fixes in fsm detect/extract for better detection of non-fsm circuits 2013-12-06 12:53:20 +01:00
hierarchy Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
memory Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
opt Improved $_MUX_ handling in opt_const 2013-12-28 10:30:31 +01:00
proc Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
sat Added sat -prove-x and -set-def-inputs 2013-12-28 11:24:36 +01:00
scc fixed typos 2013-03-18 07:28:31 +01:00
submod Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
techmap Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen) 2013-12-29 17:39:49 +01:00