mirror of https://github.com/YosysHQ/yosys.git
beedaa5856
Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file to avoid warning `DRC 23-20`. Added `open_hw` needed for programming. |
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.. | ||
README | ||
example.v | ||
example.xdc | ||
run.sh | ||
run_prog.tcl | ||
run_vivado.tcl | ||
run_yosys.ys |
README
A simple example design, based on the Digilent BASYS3 board =========================================================== This example uses Yosys for synthesis and Xilinx Vivado for place&route and bit-stream creation. Running Yosys: yosys run_yosys.ys Running Vivado: vivado -nolog -nojournal -mode batch -source run_vivado.tcl Programming board: vivado -nolog -nojournal -mode batch -source run_prog.tcl All of the above: bash run.sh