yosys/techlibs
Patrick Urban f37073050b gatemate: Update CC_PLL parameters 2023-02-14 12:02:41 +01:00
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achronix Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
anlogic anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
common Add bitwise `$bweqx` and `$bwmux` cells 2022-11-30 18:24:35 +01:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
efinix efinix: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Allow adding extra custom prims and map rules 2022-11-17 13:34:58 +01:00
gatemate gatemate: Update CC_PLL parameters 2023-02-14 12:02:41 +01:00
gowin gowin: add a new type of PLL - PLLVR 2023-01-11 11:41:29 +10:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel_alm Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
machxo2 machxo2: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
nexus nexus: Fix BRAM write enable in PDP mode 2023-01-04 17:59:36 +01:00
quicklogic Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
sf2 Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
xilinx Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00