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yosys/tests/arch/ecp5
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Marcelina Kościelnicka b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 
These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
 		2021-08-11 14:52:38 +02:00
..
.gitignore Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
add_sub.ys Share common tests 2019-10-18 12:19:59 +02:00
adffs.ys Share common tests 2019-10-18 12:19:59 +02:00
bug1459.ys Add testcase from #1459 2020-01-06 16:22:22 -08:00
bug1598.ys Add #1598 testcase 2019-12-27 16:44:57 -08:00
bug1630.il.gz Add #1630 testcase 2020-01-13 21:27:53 -08:00
bug1630.ys Update bug1630.ys to use -lut 4 instead of lut file 2020-02-27 10:17:29 -08:00
bug2409.ys memory_dff: Fix needlessly duplicating enable bits. 2020-10-22 13:03:42 +02:00
counter.ys Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
dffs.ys Share common tests 2019-10-18 12:19:59 +02:00
dpram.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
dpram.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
fsm.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
latches.ys Share common tests 2019-10-18 12:19:59 +02:00
latches_abc9.ys tests: tidy up testcase 2020-06-03 08:41:55 -07:00
logic.ys Share common tests 2019-10-18 12:19:59 +02:00
lutram.ys memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
macc.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
macc.ys Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
memories.ys test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 2021-08-11 14:52:38 +02:00
mul.ys Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
mux.ys Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
opt_lut_ins.ys Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
rom.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
rom.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
shifter.ys Share common tests 2019-10-18 12:19:59 +02:00
tribuf.ys Share common tests 2019-10-18 12:19:59 +02:00