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gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
 		2021-03-17 21:07:20 +00:00
..
.gitignore gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Makefile.inc gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_init.py support bram initialisation 2019-09-05 17:25:51 +02:00
brams_init3.vh GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
brams_map.v add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
cells_map.v gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
cells_sim.v synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
lutrams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams_map.v Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
synth_gowin.cc Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00