mirror of https://github.com/YosysHQ/yosys.git
13 lines
507 B
Plaintext
13 lines
507 B
Plaintext
read_verilog ../common/tribuf.v
|
|
hierarchy -top tristate
|
|
proc
|
|
tribuf
|
|
flatten
|
|
synth
|
|
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd tristate # Constrain all select calls below inside the top module
|
|
# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
|
|
select -assert-count 1 t:$_TBUF_
|
|
select -assert-none t:$_TBUF_ %% t:* %D
|