yosys/passes
StefanBruens 9396678db4
Fix use-after-free in LUT opt pass
RTLIL::Module::remove(Cell* cell) calls `delete cell`.

Any subsequent accesses of `cell` then causes undefined behavior.
2020-12-22 03:23:42 +01:00
..
cmds bugpoint: add -wires option. 2020-12-07 09:24:35 +00:00
equiv use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Sign extend port connections where necessary 2020-12-18 20:33:14 -07:00
memory memory_dff: Fix needlessly duplicating enable bits. 2020-10-22 13:03:42 +02:00
opt Fix use-after-free in LUT opt pass 2020-12-22 03:23:42 +01:00
pmgen Return nice error in pmgen generated code, fixes #2482 2020-12-09 11:06:22 +01:00
proc proc: Add -nomux switch 2020-08-20 22:58:08 +02:00
sat Add #include needed to build with gcc-11 2020-11-26 06:12:12 -05:00
techmap Sign extend port connections where necessary 2020-12-18 20:33:14 -07:00
tests Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00