Clifford Wolf 5025aab8c9 Add "verilog_defines -list" and "verilog_defines -reset" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-10-21 13:35:56 +02:00
..
aiger	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
ast	Use "(id)" instead of "id" for types as temporary hack	2019-10-14 05:24:31 +02:00
blif	Fix parsing of .cname BLIF statements	2019-10-16 09:06:57 +02:00
ilang	Allow attributes on individual switch cases in RTLIL.	2019-07-08 11:34:58 +00:00
json	Update JSON front-end to process new attr/param encoding	2019-08-01 12:48:22 +02:00
liberty	stoi -> atoi	2019-08-07 11:09:17 -07:00
rpc	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
verific	Fix handling of "restrict" in Verific front-end	2019-10-21 12:39:28 +02:00
verilog	Add "verilog_defines -list" and "verilog_defines -reset"	2019-10-21 13:35:56 +02:00