riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/passes
History
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
..
abc Added module->ports 2014-08-14 16:22:52 +02:00
cmds RIP $safe_pmux 2014-08-14 11:39:46 +02:00
fsm RIP $safe_pmux 2014-08-14 11:39:46 +02:00
hierarchy Added module->ports 2014-08-14 16:22:52 +02:00
memory Various improvements in memory_dff pass 2014-08-06 14:31:38 +02:00
opt RIP $safe_pmux 2014-08-14 11:39:46 +02:00
proc Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
sat Fixed "share" for complex scenarios with never-active cells 2014-08-09 17:07:20 +02:00
techmap Added module->ports 2014-08-14 16:22:52 +02:00
tests RIP $safe_pmux 2014-08-14 11:39:46 +02:00