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11 lines
447 B
Plaintext
11 lines
447 B
Plaintext
read_verilog macc.v
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proc
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hierarchy -top top
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 41 t:SB_LUT4
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select -assert-count 6 t:SB_CARRY
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select -assert-count 7 t:SB_DFFSR
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select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D
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