read_verilog macc.v
proc
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 41 t:SB_LUT4
select -assert-count 6 t:SB_CARRY
select -assert-count 7 t:SB_DFFSR
select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D