mirror of https://github.com/YosysHQ/yosys.git
3421979f00
The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support. |
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| .. | ||
| aiger | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| verific | ||
| verilog | ||