yosys/frontends/ast
Rupert Swarbrick 3421979f00 Change the type of current_module to Module
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.

This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
2021-05-13 23:44:48 -04:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc Change the type of current_module to Module 2021-05-13 23:44:48 -04:00
ast.h Change the type of current_module to Module 2021-05-13 23:44:48 -04:00
dpicall.cc dpi: Support for chandle type 2021-01-23 22:24:31 +00:00
genrtlil.cc verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
simplify.cc verilog: fix buf/not primitives with multiple outputs 2021-03-17 11:44:03 -04:00