yosys/frontends
Eddie Hung 4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
..
aiger Add and use SigSpec::reverse() 2020-01-28 10:37:16 -08:00
ast kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
blif Fix parsing of .cname BLIF statements 2019-10-16 09:06:57 +02:00
ilang read_ilang: do bounds checking on bit indices 2019-11-27 22:24:39 +01:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
rpc kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
verific Merge pull request #1667 from YosysHQ/clifford/verificnand 2020-01-30 19:55:53 +01:00
verilog Fix partsel expr bit width handling and add test case 2020-03-08 16:12:12 +01:00