yosys/frontends
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
..
aiger Replace log_assert() with meaningful log_error() 2019-06-28 12:54:44 -07:00
ast Add "read_verilog -pwires" feature, closes #1106 2019-06-19 14:38:50 +02:00
blif Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
json Add upto and offset to JSON ports 2019-06-21 19:47:25 +02:00
liberty Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
verific Only support Symbiotic EDA flavored Verific 2019-06-02 10:14:50 +02:00
verilog Merge pull request #1147 from YosysHQ/clifford/fix1144 2019-07-03 12:30:37 +02:00