riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/sat/sizebits.ys

3 lines
62 B
Plaintext
Raw Blame History

read_verilog -sv sizebits.sv
prep; sat -verify -prove-asserts
Reference in New Issue View Git Blame Copy Permalink